Experimental characterization of short channel bulk MOSFET devices with different gate LER

Transcription

1 1 Experimental characterization of short channel bulk MOSFET devices with different gate LER SFR Workshop Nov. 14, 2 Shiying Xiong, J. Bokor EECS of UC-Berkeley Qi Xiang, Philip Fisher, Ian Dudley, Paula Rao, Haihong Wang, Bill En Advanced Micro Devices GOAL:Compare the electrical performance of of short channel bulk MOSFETs with different gate line edge roughness

2 2 Outline I. Experimental characterization of Bulk MOSFET devices with different gate LER. Splits of gate LER DC characterization of devices Device Yield Threshold voltage, DIBL Comparison of the current universal curves II. Conclusion and Milestone

3 3 Wafer # 17,18 others Splits of Gate LER Gate and LER on devices Poly gate with the largest LER Poly gate with large LER Amorphous silicon gate with slightly larger LER than the well-controlled process Well controlled gate with the smallest LER RMS_Edge (nm) up to broken lines Red: Roughened wafers Circle: a-si Wafer no. Power Spectral Density Roughened Line Normal Line Frequency (1/nm)

4 More data of nominal gate length devices Top Width (nm) RMS_Wtop (nm) Red: Roughened wafers Circle: a-si up to broken lines 18 Wafer No. Red: Roughened wafers Circle: a-si Wafer No. 4 Bot Width (nm) RMS_Wbot (nm) Red: Roughened wafers Circle: a-si up to broken lines Wafer No. Red: Roughened wafers Circle: a-si Wafer No.

5 5 Electrical Characterization Overview Large gate length devices (L P =L drawn - :.76um-.13um) % of the devices work well Small deviation of V T and Sub-threshold Swing Small gate length devices (L p < nm) Lower device yield even for well controlled gate with small LER Increased fluctuation of the device performance

6 6 L drawn =.18,.19,.,.22,.27 Yield of NMOS Percentage Yield Wafer 9: Smooth Percentage Yield Wafer : Rough L drawn (um) Very large LER harmed the yield of short gate length device (Wafer ) Irregularity: The Large LER wafer shows better yield than the wafers with smallest LER Percentage Yield L drawn (um) Wafer : Rough L drawn (um)

7 7 Yield of PMOS Percentage Yield Wafer 9: Smooth Percentage Yield Wafer : Rough L drawn (um) No yield of small gate length PMOS devices on small LER wafers could be due to boron diffusion Irregularity: The Large LER wafers show yield at the gate length where small LER wafers show no yield at all Percentage Yield L drawn (um) L drawn (um) Wafer : Rough

8 8 Threshold, DIBL.6.3 NMOS VT_linear (V) Small LER Large LER NMOS VT_SAT (V) Small LER Large LER Gate Length Gate Length.5 The devices are located at the same position on different wafers Irregularity: V T rolls off slower and DIBL increases slower on the Large LER wafer NMOS DIBL (V) w9 w1 w w Gate Length

9 9 Comparison of the Ioff-Ion Curves 1E-4 1E-4 NMOS I S,off 1E-5 1E-6 1E-7 NMOS I S,off 1E-5 1E-6 1E-7 1E-8 1E-8 1E-9 Rough Gate (W) Smooth Gate (W1) 1E-9 Rough Gate (W) Smooth Gate (W9).µ 7.µ.µ 9.µ 1.m 1.1m 1.2m.µ 7.µ.µ 9.µ 1.m 1.1m 1.2m I S,on I S,on I D,off of long channel devices was raised by junction leakage LER increases the I off on average, but not dominant

10 1 Comparison of Ioff-Ion Curves 1E-4 1E-4 PMOS I off 1E-5 1E-6 1E-7 1E-8 Smooth (W1) Rough (W) PMOS I off 1E-5 1E-6 1E-7 1E-8 Smooth (W9) Rough (W) 1E-9 25.µ 3.µ 35.µ.µ 45.µ 5.µ 55.µ.µ 65.µ I on 1E-9 25.µ 3.µ 35.µ.µ 45.µ 5.µ 55.µ.µ 65.µ I on PMOS devices show no difference caused by LER, possible reasons: Low yield of very small physical gate length devices; SD (Boron) diffusion

11 Comparison of Ioff-Ion Curves Amorphous silicon gate devices 1E-3 1E-4 NMOS I off,s 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-1 1E- Rough Gate (W17) Smooth Gate (W16) 5.µ.µ 7.µ.µ 9.µ 1.m 1.1m 1.2m 1.3m I on,s PMOS I off 1E-5 1E-6 1E-7 1E-8 1E-9 Smooth (w16) Rough (w17).µ 3.µ.µ 5.µ.µ 7.µ I on Devices show no difference: LER difference is small; other process variations

12 Conclusion The effects of gate LER on the electrical behavior of bulk MOSFET devices were studied experimentally We observed that large LER raises the off-state current of NMOS devices on average. But even with very large LER amplitude, the effect is still not dominant because of the fluctuation due to other process variation in very small gate length devices. Diffusion smoothes SD to channel junction, which reduces the difference on the current universal curves of PMOS devices for different LER. Large gate edge LER may fluctuate the the halo placement and causes abnormal variation on device performance. LER in well controlled process can be made much smaller (edge RMS <2nm), it may not be an first order factor limiting device performance around 5nm technology node Milestone Devices with different LER are made on AMD wafers Electrical characterization of devices with different gate LER