Asynchronous Circuit Design

Transcription

1 Libraries and Packages Slide 1 Asynchronous Circuit Design Chris J. Myers Lecture 2: Communication Channels Chapter 2 Slide wine example.vhd library ieee; use ieee.std logic 1164.all; use ieee.std logic arith.all; use ieee.std logic unsigned.all; use work.nondeterminism.all; use work.channel.all; Communication Channels Slide 2 Channel is used as a point-to-point means of communication between two concurrently operating processes. Channel package (see channel.vhd) includes: channel data type init channel procedure send procedure receive procedure Slide 4 entity wine example is end wine example; Entities/Architectures architecture behavior of wine example is -- declarations -- concurrent statements probe procedure 1 2

2 Signal Declarations Slide 5 type wine list is (cabernet, merlot, zinfandel, chardonnay, sauvignon blanc, pinot noir, riesling, bubbly); signal wine drunk:wine list; signal WineryShop:channel:=init channel; signal ShopPatron:channel:=init channel; signal bottle:std logic vector(2 downto 0):="000"; signal shelf:std logic vector(2 downto 0); Slide 7 Concurrent Processes: winery winery:process send(wineryshop,bottle); end process winery; signal bag:std logic vector(2 downto 0); Std Logic Values U Unitialized Slide 6 X Forcing unknown 0 Forcing 0 1 Forcing 1 Z High impedance W Weak unknown L Weak 0 Slide 8 Concurrent Processes: shop shop:process receive(wineryshop,shelf); send(shoppatron,shelf); end process shop; H Weak 1 - Don t care 3 4

3 Structural Modeling: shop.vhd entity shop is port(wine delivery:inout channel:=init channel; Slide 9 Concurrent Processes: patron patron:process receive(shoppatron,bag); wine drunk <= wine list val(conv integer(bag)); Slide 11 wine selling:inout channel:=init channel); end shop; architecture behavior of shop is signal shelf:std logic vector(2 downto 0); shop:process end process patron; receive(wine delivery,shelf); send(wine selling,shelf); end process shop; Structural Modeling: winery.vhd entity winery is port(wine shipping:inout channel:=init channel); end winery; Slide 10 Winery Block Diagram for wine shop WineryShop ShopPatron Shop Patron Slide 12 architecture behavior of winery is signal bottle:std logic vector(2 downto 0):="000"; winery:process send(wine shipping,bottle); end process winery; 5 6

4 Structural Modeling: patron.vhd Slide 13 entity patron is port(wine buying:inout channel:=init channel); end patron; architecture behavior of patron is type wine list is (cabernet,merlot,zinfandel,chardonnay, sauvignon blanc,pinot noir,riesling,bubbly); signal wine drunk:wine list; signal bag:std logic vector(2 downto 0); patron:process receive(wine buying,bag); wine drunk <= wine list val(conv integer(bag)); end process patron; Slide 15 Component Declarations component winery port(wine shipping:inout channel); end component; component shop port(wine delivery:inout channel; wine selling:inout channel); end component; component patron port(wine buying:inout channel); end component; signal WineryShop:channel:=init channel; signal ShopPatron:channel:=init channel; Structural Modeling: wine example2.vhd Slide wine example2.vhd library ieee; use ieee.std logic 1164.all; use work.nondeterminism.all; use work.channel.all; entity wine example is end wine example; architecture structure of wine example is -- component and signal declarations -- component instantiations Slide 16 Component Instantiations THE WINERY:winery port map(wine shipping => WineryShop); THE SHOP:shop port map(wine delivery => WineryShop, wine selling => ShopPatron); THE PATRON:patron port map(wine buying => ShopPatron); end structure; end structure; 7 8

5 Block Diagram Including New Wine Shop Slide 17 Block Diagram Including New Wine Shop Slide 19 WineryOldShop OldShop OldShopPatron Winery WineryShop OldShop ShopNewShop NewShop NewShopPatron Patron Winery WineryNewShop NewShop NewShopPatron Patron VHDL with New Wine Shop Slide 18 architecture new structure of wine example is -- component declarations -- channel declarations -- winery OLD SHOP:shop port map(wine delivery => WineryShop, NEW SHOP:shop wine selling => ShopNewShop); port map(wine delivery => ShopNewShop, -- patron wine selling => NewShopPatron); Slide 20 Deterministic Selection: if-then-else winery2:process if (wine list val(conv integer(bottle)) = merlot) then send(winerynewshop,bottle); else send(wineryoldshop,bottle); end if; end process winery2; end new structure; 9 10

6 Slide 21 winery3:process Deterministic Selection: case case (wine list val(conv integer(bottle))) is when merlot => send(winerynewshop,bottle); when others => send(wineryoldshop,bottle); end case; end process winery3; Slide 23 Non-deterministic Selection: case winery5:process variable z:integer; z:=selection(2); case z is when 1 => send(winerynewshop,bottle); when others => send(wineryoldshop,bottle); end case; end process winery5; Slide 22 Non-deterministic Selection: if-then-else winery4:process variable z:integer; z:=selection(2); if (z = 1) then send(winerynewshop,bottle); else send(wineryoldshop,bottle); end if; end process winery4; Slide 24 Repetition: for loops winery6:process for i in 1 to 4 loop send(wineryoldshop,bottle); end loop; for i in 1 to 3 loop send(winerynewshop,bottle); end loop; end process winery6; 11 12

7 Slide 25 Repetition: while loops winery7:process while (wine list val(conv integer(bottle)) /= merlot) loop Slide 27 Deadlock producer:process send(x,x); send(y,y); end process producer; send(wineryoldshop,bottle); end loop; send(winerynewshop,bottle); end process winery7; consumer:process receive(y,a); receive(x,b); end process consumer; Repetition: infinite loops The Probe winery8:process patron2:process Slide 26 send(wineryoldshop,bottle); loop Slide 28 if (probe(oldshoppatron)) then receive(oldshoppatron,bag); wine drunk <= wine list val(conv integer(bag)); elsif (probe(newshoppatron)) then receive(newshoppatron,bag); wine drunk <= wine list val(conv integer(bag)); send(winerynewshop,bottle); end loop; end process winery8; end if; end process patron2; 13 14

8 MiniMIPS: ISA Instruction Operation Example Parallel Send add rd := rs + rt add r1, r2, r3 Slide 29 winery9:process bottle1 <= selection(8,3); bottle2 <= selection(8,3); send(wineryoldshop,bottle1,winerynewshop,bottle2); end process winery9; Slide 31 sub rd := rs rt sub r1, r2, r3 and rd := rs & rt and r1, r2, r3 or rd := rs rt or r1, r2, r3 lw rt := mem[rs + offset] lw r1, (32)r2 sw mem[rs + offset] := rt sw r1, (32)r2 beq if (rs==rt) then beq r1, r2, Loop PC := PC + offset j PC := address j Loop MiniMIPS: ISA Instruction Opcode Func Slide 30 Parallel Receive patron3:process receive(oldshoppatron,bag1,newshoppatron,bag2); wine drunk1 <= wine list val(conv integer(bag1)); wine drunk2 <= wine list val(conv integer(bag2)); end process patron3; Slide 32 add 0 32 sub 0 34 and 0 36 or 0 37 lw 35 n/a sw 43 n/a beq 4 n/a j 6 n/a 15 16

9 MiniMIPS: Instruction Formats Block Diagram for MiniMIPS Register instructions opcode rs rt rd shamt func branch_decision decode_instr address PC imem_address data new_instr imem_data bd instr imem fetch Slide 33 Load/store/branch instructions opcode rs rt offset Jump instructions opcode address 6 26 Slide 35 decode_instr execute_op execute_rs execute_rt execute_rd execute_func execute_offset dmem_datain dmem_dataout decode op rs rt rd func offset datain execute_op execute_rs execute_rt execute_rd execute_func data_out execute_offset data_in dmem_addr addr address dmem_rv read_write read_write branch_decision dmem execute dataout MiniMIPS: minimips.vhd Slide 34 Block Diagram for MiniMIPS imem fetch decode execute dmem Slide Entity/architecture declarations -- ieee stuff use work.channel.all; entity minimips is end minimips; architecture structure of minimips is -- Component declarations -- Signal declarations -- Component instantiations end structure; 17 18

10 MiniMIPS: imem.vhd -- ieee stuff use work.nondeterminism.all; Slide 37 use work.channel.all; entity imem is port(address:inout channel:=init channel; end imem; data:inout channel:=init channel); architecture behavior of imem is type memory is array (0 to 7) of std logic vector(31 downto 0); Slide 39 MiniMIPS: fetch.vhd entity fetch is port(imem address:inout channel:=init channel; imem data:inout channel:=init channel; decode instr:inout channel:=init channel; branch decision:inout channel:=init channel); end fetch; signal addr:std logic vector(31 downto 0); signal instr:std logic vector(31 downto 0); MiniMIPS: imem.vhd MiniMIPS: fetch.vhd process variable imem:memory:=( architecture behavior of fetch is signal PC:std logic vector(31 downto 0):=(others=> 0 ); X"8c220000", -- L: lw r2,0(r1) signal instr:std logic vector(31 downto 0);...);-- j M signal bd:std logic; Slide 38 receive(address,addr); instr <= imem(conv integer(addr(2 downto 0))); send(data,instr); end process; Slide 40 alias opcode:std logic vector(5 downto 0) is instr(31 downto 26); alias offset:std logic vector(15 downto 0) is instr(15 downto 0); alias address:std logic vector(25 downto 0) is instr(25 downto 0); 19 20

11 MiniMIPS: fetch.vhd MiniMIPS: decode.vhd Slide 41 process variable branch offset:std logic vector(31 downto 0); send(imem address,pc); receive(imem data,instr); PC <= PC + 1; case opcode is when "000110" => -- j PC <= (PC(31 downto 26) & address); Slide 43 entity decode is port(decode instr:inout channel:=init channel; execute op:inout channel:=init channel; execute rs:inout channel:=init channel; execute rt:inout channel:=init channel; execute rd:inout channel:=init channel; execute func:inout channel:=init channel; execute offset:inout channel:=init channel; dmem datain:inout channel:=init channel; dmem dataout:inout channel:=init channel); end decode; Slide 42 MiniMIPS: fetch.vhd when "000100" => -- beq send(decode instr,instr); receive(branch decision,bd); if (bd = 1 ) then branch offset(31 downto 16):=(others=>instr(15)); branch offset(15 downto 0):=offset; PC <= PC + branch offset; end if; when others => send(decode instr,instr); end case; end process; Slide 44 MiniMIPS: decode.vhd type reg array is array (0 to 7) of std logic vector(31 downto 0); signal instr:std logic vector(31 downto 0); alias op:std logic vector(5 downto 0) is instr(31 downto 26); alias rs:std logic vector(2 downto 0) is instr(23 downto 21); alias rt:std logic vector(2 downto 0) is instr(18 downto 16); alias rd:std logic vector(2 downto 0) is instr(13 downto 11); alias func:std logic vector(5 downto 0) is instr(5 downto 0); alias offset:std logic vector(15 downto 0) is instr(15 downto 0); signal registers:reg array:=(x" ",...); signal reg rs:std logic vector(31 downto 0); signal reg rt:std logic vector(31 downto 0); signal reg rd:std logic vector(31 downto 0); 21 22

12 MiniMIPS: decode.vhd process Slide 45 receive(decode instr,instr); reg rs <= reg(conv integer(rs)); reg rt <= reg(conv integer(rt)); send(execute op,op); case op is when "000000" => -- ALU op send(execute func,func,execute rs,reg rs, execute rt,reg rt); Slide 47 MiniMIPS: decode.vhd when others => -- undefined assert false report "Illegal instruction" severity error; end case; end process; receive(execute rd,reg rd); reg(conv integer(rd)) <= reg rd; Slide 46 MiniMIPS: decode.vhd when "000100" => -- beq send(execute rs,reg rs,execute rt,reg rt); when "100011" => -- lw send(execute rs,reg rs,execute offset,offset); receive(dmem dataout,reg rt); reg(conv integer(rt)) <= reg rt; when "101011" => -- sw send(execute rs,reg rs,execute offset,offset, dmem datain,reg rt); Slide 48 MiniMIPS: execute.vhd entity execute is port(execute op:inout channel:=init channel; execute rs:inout channel:=init channel; execute rt:inout channel:=init channel; execute rd:inout channel:=init channel; execute func:inout channel:=init channel; execute offset:inout channel:=init channel; dmem addr:inout channel:=init channel; dmem rw:inout channel:=init channel; branch decision:inout channel:=init channel); end execute; 23 24

13 MiniMIPS: execute.vhd Slide 49 MiniMIPS: execute.vhd architecture behavior of execute is signal rs:std logic vector(31 downto 0); signal rt:std logic vector(31 downto 0); signal rd:std logic vector(31 downto 0); signal op:std logic vector(5 downto 0); signal func:std logic vector(5 downto 0); signal offset:std logic vector(15 downto 0); signal rw:std logic; signal bd:std logic; Slide 51 when "000000" => -- ALU op receive(execute func,func,execute rs,rs,execute rt,rt); case func is when "100000" => -- add rd <= rs + rt; when "100010" => -- sub rd <= rs - rt; when "100100" => -- and rd <= rs and rt; when "100101" => -- or rd <= rs or rt; when others => rd <= (others => X ); -- undefined end case; send(execute rd,rd); MiniMIPS: execute.vhd Slide 50 process variable addr offset:std logic vector(31 downto 0); receive(execute op,op); case op is when "000100" => -- beq receive(execute rs,rs,execute rt,rt); if (rs = rt) then bd <= 1 ; else bd <= 0 ; end if; Slide 52 MiniMIPS: execute.vhd when "100011" => -- lw receive(execute rs,rs,execute offset,offset); addr offset(31 downto 16):=(others => offset(15)); addr offset(15 downto 0):=offset; rd <= rs + addr offset; rw <= 1 ; send(dmem addr,rd); send(dmem rw,rw); send(branch decision,bd); 25 26

14 Slide 53 MiniMIPS: execute.vhd when "101011" => -- sw receive(execute rs,rs,execute offset,offset); addr offset(31 downto 16):=(others => offset(15)); addr offset(15 downto 0):=offset; rd <= rs + addr offset; rw <= 0 ; send(dmem addr,rd); send(dmem rw,rw); when others => -- undefined assert false report "Illegal instruction" severity error; end case; end process; Slide 55 receive(address,addr); MiniMIPS: dmem.vhd receive(read write,rw); case rw is when 1 => d <= dmem(conv integer(addr(2 downto 0))); send(data out,d); when 0 => receive(data in,d); dmem(conv integer(addr(2 downto 0))) <= d; when others => end case; MiniMIPS: dmem.vhd entity dmem is port(address:inout channel:=init channel; data in:inout channel:=init channel; Slide 54 end dmem; data out:inout channel:=init channel; read write:inout channel:=init channel); architecture behavior of dmem is type memory is array (0 to 7) of std logic vector(31 downto 0); signal addr:std logic vector(31 downto 0); Slide 56 r1 contains 1. r2 contains 2. add r1,r2,r2 add r4,r1,r1 RAW Hazards signal d:std logic vector(31 downto 0); signal rw:std logic; signal dmem:memory:=(x" ",...); 27 28

15 Slide 57 Pipelined MiniMIPS: decode.vhd signal reg locks:booleans(0 to 7):=(others => false); signal decode to wb:channel:=init channel; signal wb instr:std logic vector(31 downto 0); alias wb op:std logic vector(5 downto 0) is wb instr(31 downto 26); alias wb rt:std logic vector(2 downto 0) is wb instr(18 downto 16); alias wb rd:std logic vector(2 downto 0) is wb instr(13 downto 11); signal lock:channel:=init channel; Slide 59 Pipelined MiniMIPS: decode.vhd when "000000" => -- ALU op send(execute func,func,execute rs,reg rs, execute rt,reg rt); send(decode to wb,instr); receive(lock); when "100011" => -- lw send(execute rs,reg rs,execute offset,offset); send(decode to wb,instr); receive(lock); Pipelined MiniMIPS: decode.vhd Pipelined MiniMIPS: decode.vhd writeback:process receive(decode instr,instr); if ((reg locks(conv integer(rs))) or receive(decode to wb,wb instr); case wb op is (reg locks(conv integer(rt)))) then when "000000" => -- ALU op Slide 58 wait until ((not reg locks(conv integer(rs))) and (not reg locks(conv integer(rt)))); end if; reg rs <= reg(conv integer(rs)); reg rt <= reg(conv integer(rt)); send(execute op,op); Slide 60 reg locks(conv integer(wb rd)) <= true; wait for 1 ns; send(lock); receive(execute rd,reg rd); reg(conv integer(wb rd)) <= reg rd; reg locks(conv integer(wb rd)) <= false; 29 30

16 Pipelined MiniMIPS: decode.vhd when "100011" => -- lw reg locks(conv integer(wb rt)) <= true; wait for 1 ns; send(lock); receive(dmem dataout,reg rd); Slide 61 reg(conv integer(wb rt)) <= reg rd; Slide 63 This page blank reg locks(conv integer(wb rt)) <= false; when others => -- undefined end case; end process; Summary Channel package Send and receive procedures Slide 62 Structural modeling Selection and repetition Slide 64 This page blank The probe Parallel composition MiniMIPS 31 32