Synchronous Systems. Asynchronous Circuit Design. Synchronous Disadvantages. Synchronous Advantages. Asynchronous Advantages. Asynchronous Systems

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1 Synchronous Systems Asynchronous ircuit Design All events are synchronized to a single global clock. INPUTS hris J. Myers Lecture 1: Introduction Preface and hapter 1 omb. Logic Register OUTPUTS STATE LOK hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 1 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 2 / 1 Synchronous Advantages Synchronous Disadvantages Simple way to implement sequencing. Widely taught and understood. Available components. Simple way to deal with noise and hazards. lock distribution is difficult due to clock skew. Worst-case design. Sensitive to variations in physical parameters. Not modular. Power consumption. hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 3 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 4 / 1 Asynchronous Systems Asynchronous Advantages Synchronization is achieved without a global clock. INPUTS omb. Logic Delay OUTPUTS Elimination of clock distribution problems. Average-case performance. Adaptivity to processing and environmental variations. omponent modularity. Lower system power requirements. STATE hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 5 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 6 / 1

2 Asynchronous hallenges Asynchronous ircuit History Lack of mature computer-aided design tools. Large area overhead for the removal of hazards. Average-case delay can be large. Lack of designer eperience. Every design method traces its roots to one of two individuals: Huffman - fundamental-mode circuits. Muller - speed-independent circuits. hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 7 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 8 / 1 Key Asynchronous ircuit Designs Asynchronous Startups ILLIA (1952) and ILLA2 (1962) - U. of Illinois Atlas (1962) and MU-5 (1966) - U. of Manchester Macromodules (60s-70s) - Washington U., St. Louis First commercial graphics system (70s) - Evans & Sutherland DDM dataflow computer (1978) - U. of Utah First asynchronous microprocessor (1989) - altech First code-compatible processor (1994) - U. of Manchester ommercial pager (90s) - Phillips RAPPID (1995-9) - Intel Handshake Solutions - Microcontrollers (Phillips) Fulcrum - Ethernet Switches (altech) Silisti - Self-timed interconnect (U. of Manchester) Achroni Semiconductor - Asynchronous FPGAs (ornell) hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 9 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 10 / 1 Wine Shop Problem Specification hannels of ommunication Small winery and wine shop in Southern Utah. Only a single wine patron. Wine shop only has a single small shelf. Winery WineryShop Shop ShopPatron Patron Synchronous versus asynchronous wine shopping. hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 11 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 12 / 1

3 hannels of ommunication in VHDL Event Protocol Winery:process send(wineryshop,bottle); Shop:process receive(wineryshop,shelf); send(shoppatron,shelf); Patron:process receive(shoppatron,bag); Shop:process ; - call winery ; - wine arrives ; - call patron ; - patron buys wine hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 13 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 14 / 1 Signal Protocol 2-Phase Protocol Shop:process assign(, 1 ); - call winery guard(, 1 ); - wine arrives assign(, 1 ); - call patron guard(, 1 ); - patron buys wine Shop_2Phase:process assign(, 1 ); - call winery guard(, 1 ); - wine arrives assign(, 1 ); - call patron guard(, 1 ); - patron buys wine assign(, 0 ); - call winery guard(, 0 ); - wine arrives assign(, 0 ); - call patron guard(, 0 ); - patron buys wine hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 15 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 16 / 1 Waveform for 2-Phase Protocol 4-Phase Protocol: Active/Active Shop_4Phase:process assign(, 1 ); - call winery guard(, 1 ); - wine arrives assign(, 0 ); - reset guard(, 0 ); - resets assign(, 1 ); - call patron guard(, 1 ); - patron buys wine assign(, 0 ); - reset guard(, 0 ); - resets hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 17 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 18 / 1

4 Waveform for 4-Phase Protocol 4-Phase Protocol: Passive/Active Shop_PA:process guard(, 1 ); - winery calls assign(, 1 ); - wine is received guard(, 0 ); - resets assign(, 0 ); - reset assign(, 1 ); - call patron guard(, 1 ); - patron buys wine assign(, 0 ); - reset guard(, 0 ); - resets hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 19 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 20 / 1 4-Phase Protocol: Passive/Passive Active/Active Protocol Shop_AA:process assign(, 1 ); - call winery guard(, 1 ); - wine arrives assign(, 0 ); - reset guard(, 0 ); - resets assign(, 1 ); - call patron guard(, 1 ); - patron buys wine assign(, 0 ); - reset guard(, 0 ); - resets hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 21 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 22 / 1 Active/Active Reshuffled Active/Active ircuit Shop_AA_reshuffled:process assign(, 1 ); - call winery guard(, 1 ); - wine arrives assign(, 1 ); - call patron guard(, 1 ); - patron buys wine assign(, 0 ); - reset guard(, 0 ); - resets assign(, 0 ); - reset guard(, 0 ); - resets hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 23 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 24 / 1

5 Passive/Active Reshuffled Passive/Active ircuit Shop_PA_reshuffled:process guard(, 1 ); - winery calls assign(, 1 ); - receives wine guard(, 0 ); - resets assign(, 1 ); - call patron guard(, 0 ); - resets assign(, 0 ); - reset guard(, 1 ); - patron buys wine assign(, 0 ); - reset hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 25 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 26 / 1 AFSM and Huffman Flow Table (A/A reshuffled) Petri-net (P/A reshuffled) + / 0 1, 10 0, , 10 2, , 01 2, , 00 3, 01 / hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 27 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 28 / 1 Petri-net (P/A reshuffled) Petri-net (P/A reshuffled) hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 29 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 30 / 1

6 TEL Structure (P/A reshuffled) A/A Reshuffled ircuit + [] - [~] + [~] [] + - [] + [~] - [~] - [] hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 31 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 32 / 1 P/A Reshuffled ircuit Active/Active State Variable Shop_AA_state_variable:process assign(, 1 ); - call winery guard(, 1 ); - wine arrives assign(, 1 ); - set state variable assign(, 0 ); - reset guard(, 0 ); - resets assign(, 1 ); - call patron guard(, 1 ); - patron buys wine assign(, 0 ); - reset state variable assign(, 0 ); - reset guard(, 0 ); - resets hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 33 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 34 / 1 A/A SV ircuit AFSM and Huffman Flow Table (A/A SV) u6 u5 u1 u3 u4 u2 / 0 1, 0 0, , 10 2, 0 2 3, 0 2, , 01 0, 0 / +, +, +, -, -, +, + u2-, -, u6- glitches! hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 35 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 36 / 1

7 Reduced AFSM and Huffman Flow Table (A/A SV) Karnaugh Maps for Huffman s A/A SV ircuit / 0 0, 10 0, 00 1, 0 1 1, 01 0, 0 1, 00 / / / / hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 37 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 38 / 1 Huffman s A/A SV ircuit Huffman s Assumptions X u5 u1 u4 u6 u2 u7 u3 Bounded gate and wire delay model. ircuit does not need to be closed. Single-input change fundamental mode. One input changes output changes state changes. May need to add delay in fed back state variables. hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 39 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 40 / 1 Huffman s A/A SV ircuit Muller s Active/Active SV ircuit X u1 u4 u6 u2 u7 u3 u5 +, +, X+, +, -, -, +, + will not go low until after both u2- and u6- due to feedback delay assumption. hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 41 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 42 / 1

8 Muller s Assumptions Muller s Active/Active SV ircuit Unbounded gate delay model. Wire delays are assumed to be negligible. Forks are assumed to be isochronic. Model called speed-independent. +, +, +, -, -, +, + change felt at both and gates simultaneously due to isochronic fork assumption. hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 43 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 44 / 1 Timed Wine Shop Timed Winery and Patron Shop_AA_timed:process assign(, 1,0,1); - call winery assign(, 1,0,1); - call patron - wine arrives and patron arrives guard_and(, 1,, 1 ); assign(, 0,0,1); assign(, 0,0,1); - wait for and to reset guard_and(, 0,, 0 ); winery:process guard(, 1 ); - wine requested assign(, 1,2,3); - deliver wine guard(, 0 ); assign(, 0,2,3); patron:process guard(, 1 ); - shop called assign(, 1,5,inf); - buy wine guard(, 0 ); assign(, 0,5,7); hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 45 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 46 / 1 TEL Structure for Timed Wine Shop Eample State Graph for Timed Wine Shop Eample + [2,3] [~] - + [5,7] [~] [2,3] [] [5,inf] [] + [ & ] [~ & ~] R01R F10F R0-0F00 - FF00 RR11 + 1R F1 - - State vector: (,,, ) hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 47 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 48 / 1

9 Karnaugh Maps for Timed ircuit Timed ircuit / / / [2,3] [5,inf; 5,7] hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 49 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 50 / 1 Performance Analysis Validation versus Verification ycle time is the delay from when the patron gets one bottle of wine until he can get another. Assuming the timed circuit delays are uniformly distributed ecept that the patron is etremely unlikely to take more then 10 minutes, we obtain the following cycle times: Muller and Huffman s circuits (A/A SV) minutes Original (A/A reshuffled) minutes Timed circuit minutes Validation is simulation of interesting situations. Verification is ehaustive checks of all possible situations. an check that circuit conforms to the specification. an check that protocol has certain properties. hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 51 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 52 / 1 Sample Properties Summary of ourse Topics The wine arrives before the patron: Always( ) When the wine is requested, it eventually arrives: Eventually() ommunication hannels ommunication Protocols Graphical Representations Huffman ircuits Muller ircuits Timed ircuits Verification Applications hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 53 / 1 hris J. Myers (Lecture 1: Introduction) Asynchronous ircuit Design 54 / 1