Asynchronous Circuit Design

Transcription

1 Asynchronous Circuit Design Synchronous Advantages Slide 1 Chris J. Myers Lecture 1: Introduction Preface and Chapter 1 Slide 3 Simple way to implement sequencing. Widely taught and understood. Available components. Simple way to deal with noise and hazards. Synchronous Systems All events are synchronized to a single global clock. Synchronous Disadvantages Clock distribution is difficult due to clock skew. Slide 2 INPUTS Comb. Logic Register OUTPUTS Slide 4 Worst-case design. Sensitive to variations in physical parameters. Not modular. STATE Power consumption. CLOCK 1 2

2 Slide 5 Asynchronous Systems Synchronization is achieved without a global clock. INPUTS Slide 7 Asynchronous Challenges Lack of mature computer-aided design tools. Large area overhead for the removal of hazards. Comb. Logic Delay OUTPUTS STATE Average-case delay can be large. Lack of designer experience. Asynchronous Advantages Elimination of clock distribution problems. Asynchronous Circuit History Slide 6 Average-case performance. Adaptivity to processing and environmental variations. Slide 8 Every design method traces its roots to one of two individuals: Huffman - fundamental-mode circuits. Component modularity. Muller - speed-independent circuits. Lower system power requirements. 3 4

3 Key Asynchronous Circuit Designs ILLIAC (1952) and ILLAC2 (1962) - U. of Illinois Atlas (1962) and MU-5 (1966) - U. of Manchester Slide 9 Macromodules (60s-70s) - Washington U., St. Louis First commercial graphics system (70s) - Evans & Sutherland DDM dataflow computer (1978) - U. of Utah Slide 11 Winery Channels of Communication WineryShop ShopPatron Shop Patron First asynchronous microprocessor (1989) - Caltech First code-compatible processor (1994) - U. of Manchester Commercial pager (90s) - Phillips RAPPID (1995-9) - Intel Channels of Communication in VHDL Winery:process Slide 10 Wine Shop Problem Specification Small winery and wine shop in Southern Utah. Only a single wine patron. Wine shop only has a single small shelf. Slide 12 send(wineryshop,bottle); Shop:process receive(wineryshop,shelf); send(shoppatron,shelf); Synchronous versus asynchronous wine shopping. Patron:process receive(shoppatron,bag); 5 6

4 2-Phase Protocol Event Protocol Shop 2Phase:process Slide 13 Shop:process req wine; -- call winery ack wine; -- wine arrives req patron; -- call patron ack patron; -- patron buys wine Slide 15 assign(req wine, 1 ); -- call winery guard(ack wine, 1 ); -- wine arrives assign(req wine, 0 ); -- call winery guard(ack wine, 0 ); -- wine arrives assign(req patron, 0 ); -- call patron guard(ack patron, 0 ); -- patron buys wine Signal Protocol Waveform for 2-Phase Protocol Shop:process Slide 14 assign(req wine, 1 ); guard(ack wine, 1 ); -- call winery -- wine arrives Slide

5 4-Phase Protocol: Active/Active 4-Phase Protocol: Passive/Active Slide 17 Shop 4Phase:process assign(req wine, 1 ); -- call winery guard(ack wine, 1 ); -- wine arrives assign(req wine, 0 ); -- reset req wine guard(ack wine, 0 ); -- ack wine resets assign(req patron, 0 ); -- reset req patron guard(ack patron, 0 ); -- ack patron resets Slide 19 Shop PA:process guard(req wine, 1 ); -- winery calls assign(ack wine, 1 ); -- wine is received guard(req wine, 0 ); -- req wine resets assign(ack wine, 0 ); -- reset ack wine assign(req patron, 0 ); -- reset req patron guard(ack patron, 0 ); -- ack patron resets 4-Phase Protocol: Passive/Passive Waveform for 4-Phase Protocol Slide 18 Slide

6 Active/Active Reshuffled Passive/Active Reshuffled Slide 21 Shop AA reshuffled:process assign(req wine, 1 ); -- call winery guard(ack wine, 1 ); -- wine arrives assign(req wine, 0 ); -- reset req wine guard(ack wine, 0 ); -- ack wine resets assign(req patron, 0 ); -- reset req patron guard(ack patron, 0 ); -- ack patron resets Slide 23 Shop PA reshuffled:process guard(req wine, 1 ); -- winery calls assign(ack wine, 1 ); -- receives wine guard(ack patron, 0 ); -- ack patron resets guard(req wine, 0 ); -- req wine resets assign(ack wine, 0 ); -- reset ack wine assign(req patron, 0 ); -- reset req patron Passive/Active Circuit Active/Active Circuit Slide 22 Slide 24 C C 11 12

7 AFSM and Huffman Flow Table (A/A reshuffled) TEL Structure (P/A reshuffled) 0 ack wine / ack patron + + Slide 25 00/ / / / , 10 0, , 10 2, , 01 2, , 00 3, 01 req wine / req patron Slide 27 [] + [~] - [~] [] - [~] + [~] - [] [] Petri-net (P/A reshuffled) + A/A Reshuffled Circuit Slide Slide

8 P/A Reshuffled Circuit A/A SV Circuit Slide 29 C C Slide 31 u5 u1 u3 C u4 x u6 u2 Slide 30 Active/Active State Variable Shop AA state variable:process assign(req wine, 1 ); -- call winery guard(ack wine, 1 ); -- wine arrives assign(x, 1 ); -- set state variable assign(req wine, 0 ); -- reset req wine guard(ack wine, 0 ); -- ack wine resets assign(x, 0 ); -- reset state variable assign(req patron, 0 ); -- reset req patron guard(ack patron, 0 ); -- ack patron resets Slide 32 AFSM and Huffman Flow Table (A/A SV) 0 00/ /00 01/ /01 3 ack wine / ack patron , 0 0, , 10 2, 0 2 3, 0 2, , 01 0, 0 req wine / req patron 15 16

9 Reduced AFSM and Huffman Flow Table (A/A SV) Huffman s A/A SV Circuit Slide / /10 01/00 00/01 ack wine / ack patron , 10 0, 00 1, 0 1 1, 01 0, 0 1, 00 req wine / req patron Slide 35 X u5 u1 u4 u6 u2 u7 u3 x Karnaugh Maps for Huffman s A/A SV Circuit ack wine/ack patron x ack wine/ack patron x Huffman s Assumptions Bounded gate and wire delay model. Slide req wine req patron ack wine/ack patron x Slide 36 Circuit does not need to be closed. Single-input change fundamental mode. One input changes output changes state changes. May need to add delay in fed back state variables x 17 18

10 Muller s Active/Active SV Circuit Timed Wine Shop Shop AA timed:process Slide 37 x Slide 39 assign(req wine, 1,0,1); -- call winery assign(req patron, 1,0,1); -- call patron -- wine arrives and patron arrives guard and(ack wine, 1,ack patron, 1 ); x assign(req wine, 0,0,1); assign(req patron, 0,0,1); -- wait for ack wine and ack patron to reset guard and(ack wine, 0,ack patron, 0 ); Timed Winery and Patron winery:process guard(req wine, 1 ); -- wine requested Muller s Assumptions assign(ack wine, 1,2,3); -- deliver wine Slide 38 Unbounded gate delay model. Wire delays are assumed to be negligible. Forks are assumed to be isochronic. Model called speed-independent. Slide 40 guard(req wine, 0 ); assign(ack wine, 0,2,3); patron:process guard(req patron, 1 ); -- shop called assign(ack patron, 1,5,inf); -- buy wine guard(req patron, 0 ); assign(ack patron, 0,5,7); 19 20

11 TEL Structure for Timed Wine Shop Example Karnaugh Maps for Timed Circuit Slide 41 + [2,3] [~] + [5,7] [~] [2,3] [] [5,inf] [] [0,1] [0,1] [ & ] [0,1] - - [0,1] [~ & ~] Slide 43 req wine/ req patron ack wine/ack patron req wine ack wine/ack patron req patron State Graph for Timed Wine Shop Example Timed Circuit Slide 42 + R01R + 00R0 - RR11 + Slide 44 [0,1] [5,inf; 5,7] 0F00 1R11 [0,1] - + [2,3] FF F10F 11F

12 Performance Analysis Slide 45 Cycle time is the delay from when the patron gets one bottle of wine until he can get another. Assuming the timed circuit delays are uniformly distributed except that the patron is extremely unlikely to take more then 10 minutes, we obtain the following cycle times: Muller and Huffman s circuits (A/A SV) minutes Original (A/A reshuffled) minutes Slide 47 Sample Properties The wine arrives before the patron: Always(ack patron ack wine) When the wine is requested, it eventually arrives: req wine Eventually(ack wine) Timed circuit minutes Summary of Course Topics Communication Channels Validation versus Verification Communication Protocols Slide 46 Validation is simulation of interesting situations. Verification is exhaustive checks of all possible situations. Slide 48 Graphical Representations Huffman Circuits Can check that circuit conforms to the specification. Muller Circuits Can check that protocol has certain properties. Timing Circuits Verification Applications 23 24